1. Technical Field
The invention relates to the protection of integrated electronic circuits from ESD (Electrostatic Discharge).
It relates in general to the design of integrated electronic circuits, and more particularly to the tests used to assist with circuit design, particularly ESD sensitivity tests.
2. Description of the Related Art
These tests are intended to evaluate the robustness of integrated electronic circuits when they are exposed to electrostatic discharge, and to find design rules to limit the stresses related to such electrostatic discharge.
For determining the sensitivity of integrated electronic circuits to electrostatic discharge, there are standardized models representing the hostile environment in which these circuits live. These models are used during the testing phase in particular to assist with the electronic circuit design.
Electrostatic discharges can be so modeled using the Charged Device Model or CDM. The CDM is a standardized model which has the unique characteristic, unlike other known models, of representing the discharge from an integrated electronic circuit when assembled in a package. It allows taking into account, in terms of ESD sensitivity, the effect of the package in which the electronic circuit is placed. Note that in this context the package is defined in particular by the coating material, the connecting pins, the wires, the base or substrate, the glue, and of course the silicon chip.
CDM tests is understood to mean ESD sensitivity tests for integrated electronic circuits which are based on the CDM model.
The CDM tests themselves pose a problem regarding integrated electronic circuit reliability, which is accentuated by the reduction of the characteristic sizes of MOS transistors and the corresponding increase in the level of integration. During a CDM test, the circuit is exposed to electrical stress, also called CDM stress, in the form of currents of several amperes lasting for several nanoseconds, with a rise time of several dozen picoseconds. This CDM stress can result in damage to the circuit. In particular, CDM stress can result in short circuits or conversely in open circuits in the gate oxide layers of MOS transistors, in other irreversible deterioration, and in leakage currents.
In the prior art, the protection of integrated electronic circuits is done in three distinct regions: inputs, outputs, and power supplies. Basic structures which protect from ESD, optimized for each technology, are inserted into the integrated circuit to be protected (known as “in situ” protection) in a manner which:                combats positive and negative ESD discharges,        leaves unaffected the functionality of the circuit under normal operating conditions, meaning when the circuit is exposed to its operating voltage (“powered” mode),        levels high voltages and drains off the discharge current,        occupies as little space as possible, and,        does not introduce additional steps in the component manufacturing process.        
Even so, many components do not withstand the phases of the ESD sensitivity test because of irreversible damage arising from the CDM stress.
Completely independently of considerations related to CDM stress, it is known to protect the metal lines against the charge that occurs during the manufacture of an electronic circuit due to exposure to a plasma. Such exposure is one of the methods used to etch metal. This charge is known as the plasma charge and is the origin of later failures. It is perceptible for lines of a length exceeding several dozen microns. Because of their length, such lines are generally antenna lines. It is known to create a protective element based on a diode or diodes, called an “antenna diode”, in order to drain off the charges accumulated in these lines. Such an element is available in the component libraries which are available to integrated circuit designers.